A non-volatile memory device has characteristics in that data may be stored and erased by an electric operation, yet the data is not erased even when the power is turned off. Thus, the non-volatile memory device has been widely used in applications such as digital cellular phones, digital cameras, and local area network (LAN) switches. A unit cell of the non-volatile memory device may be classified into a NAND type or a NOR type. A NAND type non-volatile memory device (NAND memory) advantageously has a high integration density, and a NOR type non-volatile memory device (NOR memory) advantageously has a high operation speed. Because of these characteristics, the NAND memory has been widely used in the appliances requiring a high integration density rather than a high operation speed, whereas the NOR memory has been widely used in the appliances requiring a high operation speed rather than a high integration density.
The unit cell of the non-volatile memory device includes a tunnel oxide layer, a floating gate, a dielectric layer and a control gate that are sequentially stacked on a substrate. A threshold voltage of the unit cell is varied as electrons are transferred into or from the floating gate, and data is stored into the memory device using the variation of the threshold voltage. The transfer of electrons into the floating gate is performed by an injection of hot electrons having excessive energy from a channel into the floating gate or a Fowler-Nordheim tunneling, and the transfer of the electrons from the floating gate is performed by a Fowler-Nordheim tunneling.
Continuously performing erase and program operations using the non-volatile memory device requires a repetitive transfer of the electrons between the channel and the floating gate. Therefore, the characteristics of the substrate around the channel and the tunnel oxide layer may influence reliability and endurance of the memory device.
In particular, when an interface trap is formed between the tunnel oxide layer and the substrate, electrons may become trapped. As a result, electrons may not be sufficiently injected into the floating gate when data is stored into the memory device, and electrons may not be sufficiently discharged from the floating gate to the substrate when data is erased from the memory device. Accordingly, research has been conducted for reducing the interface traps between the tunnel oxide layer and the substrate. For example. Korean Patent Laid-Open Publication No. 2006-78858 discloses a method of processing a substrate to reduce the interface trap density. Particularly, a surface of the substrate is passivated with hydrogen (H), and accordingly, dangling bonds on the surface of the substrate are reacted with hydrogen atoms (H), to thereby produce a chemical bond of SiH or SiOH on the surface of the substrate. As a result, most of the interface traps are eliminated from the surface of the substrate.
However, when a non-volatile memory device is formed on the substrate passivated with hydrogen and is continuously operated by an injection and a discharge of electrons between the substrate and the floating gate through the channel, the chemical bond of SiH or SiOH may be broken and the hydrogen atoms of the chemical bond of SiH or SiOH may leak onto an insulation layer defining an active region of the substrate on which various conductive structures are formed (i.e. a device isolation layer). These leaked hydrogen atoms may deteriorate reliability and endurance of the non-volatile memory device.